MIPS Architecture-Based 32-Bit CPU
SystemVerilogModelSimFPGAMIPS

My senior year project in computer architecture class was to design a MIPS instruction set based multicore CPU using SystemVerilog and ModelSim.

The project consisted of four stages: single-cycle processor, 5-stage pipeline, L1 data and instruction cache, and finally combining everything together with cache coherence to form a multicore CPU. Parts of the design were also synthesized on Altera FPGA. The last three stages were completed with a lab partner.



Single Cycle Processor

Single cycle processor consisted of the following components:

At this stage, the cache is simply a pass-through.

Singlecore Design


Single Cycle Processor with Pipeline

The following components were then incorporated into the processor:

  • A five-stage pipeline with Instruction Fetch -> Decode -> Execute -> Memory Access -> Write-back
  • Hazard unit
  • Forwarding Unit
Singlecore Design
L1 Instruction and Data Cache

After the 5-stage pipeline, L1 instruction and data caches were also incorprated into the design:

In addition, the caches implemented write-back, allocate on miss, and LRU policies.

Instruction CacheData Cache
Multicore CPU with Cache Coherence

In the last part, two CPU blocks were put together along with coherence unit to construct a multicore processor:

  • Cache coherence using the MSI Protocol
  • LL/SC, a consumer/producer parallel algorithm written in MIPS assembly was used to test these two instructions
Multicore Design