The project consisted of four stages: single-cycle processor, 5-stage pipeline, L1 data and instruction cache, and finally combining everything together with cache coherence to form a multicore CPU. Parts of the design were also synthesized on Altera FPGA. The last three stages were completed with a lab partner.
Single cycle processor consisted of the following components:
At this stage, the cache is simply a pass-through.
The following components were then incorporated into the processor:
After the 5-stage pipeline, L1 instruction and data caches were also incorprated into the design:
In addition, the caches implemented write-back, allocate on miss, and LRU policies.